Advances in semiconductor fabrication and manufacturing techniques have led to extremely complex and compact semiconductor circuitry. Ever increasing numbers of transistors, gates and other types of components are being crammed into smaller and smaller silicon die sizes. The trend is towards even smaller, denser, and more complex semiconductor devices in the future.
However, one obstacle facing semiconductor designers is that physical limits are reached, wherein the p-n junctions of a semiconductor "break down." Basically, when a sufficiently high field is applied to a p-n junction, it breaks down and conducts a very large current. As the physical size of semiconductor components become smaller, they also become more susceptible to breaking down.
In order to mitigate this highly undesirable aspect, operating levels are being reduced from the present industry standard of 5 volts to a lower level of 3.3 volts. A lower operating voltage level reduces the chances of semiconductor junction break downs.
Another driving force behind changing the operating level from 5 volts to 3.3 volts is to decrease a semiconductor's power consumption. Semiconductors which can operate on less power are highly advantageous. This is especially true for use in battery powered equipment, such as laptop computers. An equivalent laptop computer fashioned from 3.3 volt semiconductors would typically operate longer than one fashioned from 5 volt semiconductors, given identical battery supplies. In other words, battery operated equipment would not have to be recharged as often if 3.3 volt, rather than 5 volt semiconductor chips, were to be implemented. Furthermore, the lifetime of a battery would be extended by adopting devices which require less power.
Consequently, the goal is to eventually phase out the 5 volt standard and to produce and support a whole family of semiconductor devices based on a 3.3 volt reference. However, this transition from 5 volts to 3.3 volts will be a long, slow, and arduous process. And even once a 3.3 volt standard is eventually recognized and supported, portable computers may be designed such that they run at a low voltage normally (i.e., 3.3 volts) and at a higher voltage when connected to a docking station (i.e., 5 volts).
Further complicating matters is the fact that, at present, there is no widely established industry bus standard based on a 3.3 volt level. Conflicting bus architectures and formats could cause incompatibilities between various 3.3 volt devices. It will take some time to develop a specification for a 3.3 volt bus similar to the one existing for the 5 volt bus as defined by the Instrument Society of America (ISA) specification. Hence, developers face a dilemma in choosing which of the various 3.3 volt bus schemes to support.
One approach is to implement the bulk of a semiconductor chip to operate on a 3.3 volt basis, while maintaining the I/O interface at a 5 volt basis. In this manner, battery consumption is reduced, battery life is extended, and the chip is compatible with the established 5 volt ISA bus specification. In order to implement such a scheme, the 5 volt input signals must first be translated to a 3.3 volt level. After signal processing has been completed, the processed 3.3 volt signals are then translated back to a 5 volt level for output.
One prior art scheme for translating between 3.3 and 5 volts, calls for the implementation of a separate, dedicated external bus controller (EBC). The EBC is used to provide the necessary buffering, handshaking, and translation operations. In addition, the EBC also acts as an arbitrator. All input signals are received through the EBC, and all processed signals are sent through the EBC.
Implementing an EBC helps reduce the chances of latch-up. Furthermore, impact ionization problems caused by carriers gaining enough energy to excite electron-hole pairs as the electric field in a semiconductor is increased above a certain value, are minimized. Moreover, an EBC eliminates D.C. current problems. If a 3.3 volt signal is used to drive a 5 volt device, it would cause that device to draw D.C. power, since it is neither fully on nor fully off. This problem is not as serious for desktop applications, but minimizing DC current dissipation is of prime concern for laptop and notebook applications.
However, this scheme suffers from several disadvantages. These disadvantages range from increased costs due to circuit complexity and hardware overhead to increasing the physical size of the printed circuit board in order to accommodate the additional EBC chip. Furthermore, the EBC scheme mandates that a myriad of added interconnections be implemented for coupling each of the different signal paths.
Therefore, what is needed is a simple, cost-effective mechanism for translating voltage signal levels which can be implemented within a small silicon die size, while minimizing latch-up, impact ionization, and D.C. current problems. It would also be highly preferable for the translator mechanism to be adaptable so that it can be implemented on an as needed basis rather than being restricted to I/O buffers.